Upgrade to Custom ASIC


Developing a custom ASIC offers many compelling advantages. For some it is adding smarts to make a device more compelling; for others, it’s integrating a CPU and discretes onto a chip to reduce bill-of-material cost, footprint, and improve performance or protect IP. The custom ASIC process has become a much less costly and risky proposition over the last two decades. “Easy access” and “cost-effective” tools, services and IP enable development of a custom ASIC more easily and with a much lower risk.


Arm, imec.IC-link and Mentor are world leaders in the ASIC ecosystem and have joined forces to deliver a seminar for designers, engineering directors & managers and product managers to understand the latest options to deliver a product based on a custom ASIC.


The seminar will demystify the risks, explain options and explore supply chain partnership.


Who Should Attend

  • CTO’s, system architects, engineering & product directors, managers, and engineers who are
    • investigating custom ASIC to replace off-the-shelf ICs and FPGA’s, or
    • choosing embedded processors, or
    • exploring technology node and supply chain management options
    • wanting to investigate access to silicon foundries
  • Analog and mixed signal PCB and IC designers
  • Physical layout IC designers


What you will learn

  • Business, technical and cost factors influencing more companies to adopt custom ASIC to improve their product’s competitiveness and profitability
  • A detailed exploration of design process flow and cost-effective tools for ASIC development: design, simulation, physical layout & verification for manufacturability, full system verification
  • Key features of Arm’s Cortex-M0 and Cortex-M3 processors, subsystems, system IP and important physical IP
  • Arm’s DesignStart program which has a $0 upfront license fee and a new success based royalty model
  • Manufacturing process node choices and IP selection
  • Accessing Multi Project Wafers for low cost, prototype production
  • Considerations selecting design services, assembly (IC packaging) and test offering, and complete ASIC supply chain management.



Registration & breakfast is from 8.30am and the seminar formally starts at 9.30am.
A complimentary lunch is provided and the day is expected to close by 4pm.



Upgrade to Custom ASIC - Seminar



Wednesday the 15th of November 2017



Leuven, Belgium



08.30 am - 4.00 pm



8th of November BluePrint PCB Webinar
13th till 16th of November FloEFD and FloTHERM Seminar
15th of November Upgrade to Custom ASIC
26th of October Upgrade to Custom ASIC
7th of December FloEFD User Conference 2017
28th - 29th of November FloEFD Simulation Conference 2017